Logic networks - (9 cfu)
|Prof. Stefano Caselli||Tel. 0521 905724 - Fax. 0521 905723|
| ||E-mail. email@example.com|
| ||Home page. http://www.ce.unipr.it/people/caselli|
Course objective is to introduce the fundamental techniques for digital system analysis and design. Both traditional methodologies suitable for paper and pencil and algorithmic techniques adopted in industrial Design Automation flows and CAD tools are presented. Emphasis is placed on the development of problem solving capabilities, including the ability to address design problems at high level by partitioning them into subproblems and exploiting the most appropriate components and technique for individual subproblems.
Introduction to digital systems
1 - The role of digital systems. Digital representation of information.
2 - Evolution of electronic technologies.
3 - Objectives and limitations of digital systems.
Combinational logic design
1 - Review: Canonical and general logic expressions (SoP and PoS). Analysis and synthesis of fully specified logic functions based on Karnaugh maps.
2 - Other two-level logic analysis and synthesis techniques: Incompletely specified logic functions. Multiple output circuits (multiple prime implicants/implicates method). Analysis and synthesis of NAND and NOR circuits.
3 - CAD tools for combinational network design: Quine-McCluskey algorithm. Espresso. Logic simulation.
4 - Multilevel logic and integrated circuit-based design: Expression factorization and decomposition. Combinational logic design based on standard MSI and LSI parts (Multiplexers, Decoders, Demultiplexers, Encoders, ROMs, AOI components).
5 - Interconnection technologies: Three-state gates, buffers, tranceivers. Three-state based MUX and DEMUX implementation.
6 - Combinational programmable logic (ROM, PLA, PAL, GAL).
7 - Transient phenomena in combinational circuits: static and dynamic hazards.
Synchronous sequential logic design
1 - Mealy and Moore machines. Elementary logic circuits with delays and feedback. Fundamental mode operation. Clocked oepration.
2 - Basic memory elements: SR and D Latches; D, JK, and T Flip-Flops. Timing problems. Timing in synchronous circuits.
3 - Finite state automata: Automata description techniques (state diagrams, flow tables, description languages). State minimization.
4. Analysis and synthesis of synchronous sequential circuits: State encoding. Optimal and one-hot encodings. State memory implementation with Flip-Flops and Latches.
5 - The synchronous/asynchronous interface: Flip-Flops with Preset and Clear commands. Management of asynchronous and pulsed inputs in synchronous circuits.
6 - Counters and Registers: Design of binary counters, ring counters, Johnson counters, counters with arbitrary state encoding. Parallel registers and shift registers. Control inputs in counters and registers.
7 - Sequential programmable logic (CPLD, FPGA).
Asynchronous sequential logic design
1 - State diagrams and flow tables for asynchronous circuits. Fundamental mode operation and timing in asynchronous circuits.
2 - Analysis and synthesis of asynchronous sequential circuits.
3 - State minimization for asynchronous sequential circuits.
4 - State encoding: Critical races and functional hazard problems. Techniques and tools for critical races solution: adjacency graph, encoding map, multiple state transitions, multiple state assignments. Universal assignments.
5 - State realization by direct feedback and SR Latches.
6 - Asynchronous design of synchronous memory elements: D-Latch; SR, JK, and T Flip-Flops. Master-Slave architecture. Essential hazard and ones-catching problems. Edge-Triggered architecture. Integration of Preset and Clear inputs.
7 - Asynchronous control units.
Analysis and synthesis of complex digital systems
1 - Sequential circuit design based on standard integrated circuits (registers, counters, shift-registers, sequencers, MUXes, etc.).
2 - Complex circuit design by decomposition into datapath and control unit. Control unit design.
3 - Data path components and dedicated combinational components: Arithmetic circuits (adders, comparators, ALU). Transocoders. Parity and Hamming circuitry. XOR-based circuits.
4 - Design techniques for pipelined circuits.
5 - Hardware description languages.
About 10 hours will be spent in laboratory. Lab hours will be devoted to programmable logic-based digital design using industry-standard CAD tools for schematic entry, VHDL, digital simulation, mapping onto assigned programmable components.
The recommended exam modality is to undertake the two planned mid-term written tests during the teaching period. Alternatively, a single written test covering the whole course syllabus must be passed in any of the scheduled official exam dates. Administered tests comprise design and analysis exercises, possibly integrated by a few theory questions. More frequently, theory must be known and used to solve the proposed design problems.
Lecture notes from the instructor are available in the course web site after each lecture. Selected exercises and solutions are also available in the web site. For an organic covering of the discipline the student may refer to any of the books listed below. The course approach is loosely inspired by the following two books:
F. Vahid, Digital Design, John Wiley & Sons, 2007.
J.F. Wakerly, Digital Design: Principles and Practice, 4th Edition, Prentice-Hall, 2005.
C. Bolchini, C. Brandolese, F. Salice, D. Sciuto, Reti Logiche, Apogeo, 2004.
M.M. Mano, Digital Design, 3/e, Prentice Hall, 2002.
R.H. Katz, Contemporary Logic Design, 1st Edition, Addison-Wesley, 1994.
R. Laschi, Reti Logiche, Esculapio, Bologna, 1994.
Ultimo aggiornamento: 01-10-2012